1. Field
The present disclosure relates generally to phase locked loops (PLL), and in particular, to a system and method of calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL).
2. Background
Communication devices typically include a local oscillator (LO) for synchronously transmitting and receiving signals to and from other remote communication devices. Often these signals are sent or received via defined frequency channels. For selecting a particular frequency channel, the frequency of the LO is typically changed in order to properly transmit or receive the signal via the selected channel. Often a phase locked loop (PLL), such as a digital PLL (DPLL), is used to perform the change in the LO frequency.
A typical DPLL includes several digital devices, such as an input accumulator, a phase error summing device, a low pass filter (LPF) (often referred to as a “loop filter”), a digital controlled oscillator (DCO), a DCO accumulator including a latch, a time-to-digital converter (TDC), a feedback phase summing device, and other digital devices. The input accumulator generates an input phase signal. The phase error summing device generates a phase error signal indicative of a phase difference between the input phase signal and a feedback phase signal. The loop filter generates a control signal for the DCO by filtering the phase error signal. The DCO generates an output signal having a phase related to the input phase signal when the DPLL is locked. The DCO accumulator including the latch generates a signal indicative of a coarse measurement of the phase of the output signal of the DCO. The TDC generates a signal indicative of a fine measurement of the phase of the output signal of the DCO. And, the feedback summing devices sums the coarse and fine phase signals to generate the feedback phase signal.
The TDC typically comprises a chain of delay elements (e.g., inverters), a plurality of D flip-flops, and a decoder. An output clock from or derived from the output signal of the DCO is applied to the input of the chain of delay elements. The delay elements are coupled to the data input of respective D flip-flops. A reference clock is applied to the clock inputs of the D flip-flops. The Q-outputs of the D flip-flops are coupled to inputs of a decoder, such as a thermometer-to-binary decoder. The inverted reference clock is applied to the clock input of the decoder. And, the outputs of the decoder generates a binary output representing the fractional phase of the phase difference between the output clock and the reference clock.
Typically, the frequency of the output is substantially higher than the frequency of the reference clock, e.g., by a factor of 10 or more. Generally, a phase measurement takes place when an edge of the reference clock arrives. Between adjacent edges of the reference clock, the output clock is still being applied to the chain of delay elements. This causes the delay elements to needlessly consume substantial amount of power during times when a phase measurement is not being performed. Accordingly, power-on gating for the TDC has been developed to apply the output clock to the chain of delay elements only a relatively small window around the edge of the reference clock. However, due to variations in manufacturing processes, environment temperatures, and power supply voltages, the proper size for the gating window for operational and power consumption purposes is generally difficult to ascertain.